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TECHNICAL NOTE
Plug & Play Memory series
2Kbit Serial I2C BUS EEPROM For SPD DRAM Memory Module
BR34L02-W
DESCRIPTION BR34L02-W is 2Kbit Serial I2C BUS Electrically Erasable PROM (based on Serial Presence Detect) for DRAM Memory Module FEATURES 256x8 bit architecture serial EEPROM Wide operating voltage range (1.7V5.5V) Two wire serial interface High reliability connection of Au pad and Au wire Self-Timed Erase and Write Cycle Page Write Function(16byte) Write Protect Mode Write Protect 1(Onetime Rom) : 00h7Fh Write Protect 2(Hardwire WP PIN) : 00hFFh Low Power consumption Write ( 5V ) : 1.2mA (Typ.) Read ( 5V ) : 0.2mA(Typ.) Standby ( 5V ) : 0.1A(Typ.) DATA security Write protect feature (WP pin) Inhibit to WRITE at low VCC Small package ------ SSOP-B8/TSSOP-B8 High reliability fine pattern CMOS technology Endurance : 1,000,000 erase / write cycles Data retention : 40 years Filtered inputs in SCL / SDA for noise suppression Initial data FFh in all address
BR34L02-W Series Capacity Bit format 2Kbit 256x8
Type BR34L02-W
Power source voltage 1.75.5V
SSOP-B8
TSSOP-B8
Sep.2007
ABSOLUTE MAXIMUM RATING (Ta=25) Rating -0.3+6.5 300(SSOP-B8) *1 Power Dissipation Pd 330(TSSOP-B8) *2 Storage Temperature Tstg -65+125 Operating Temperature Topr -40+85 Terminal Voltage -0.3VCC+0.3 Degradation is done at 3.0mW/(*1), 3.3mW/(*2) for operation above 25 RECOMMENDED OPERATING CONDITION Parameter Supply Voltage Input Voltage Symbol VCC IN Rating 1.75.5 0VCC Unit V V Parameter Supply Voltage Symbol VCC Unit V mW V
MEMORY CELL CHARACTERISTICSTa=25, VCC=1.75.5V Parameter Write / Erase Cycle Data Retention *1 *1 Specification Min. 1,000,000 40 Typ. Max. Unit Cycles Years
*1:Not 100% TESTED DC OPERATING CHARACTERISTICS Unless otherwise specified Ta=-4085, VCC=1.75.5V Specification Min. 0.7 VCC 0.8 VCC -1 -1 -1 Typ. Max. 0.3 VCC 0.2 VCC 0.4 0.2 1 15 1 2.0
Parameter "H" Input Voltage 1 "L" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2 Input Leakage Current 1 Input Leakage Current 2 Output Leakage Current
Symbol VIH1 VIL1 VIH2 VIL2 VOL1 VOL2 ILI1 ILI2 ILO ICC1
Unit V V V V V V A A A mA
Test Condition 2.5VVCC5.5V 2.5VVCC5.5V 1.7VVCC2.5V 1.7VVCC2.5V IOL=3.0mA2.5VVCC5.5VSDA IOL=0.7mA1.7VVCC2.5VSDA VIN=0VVCCA0,A1,A2,SCL VIN=0VVCCWP VOUT=0VVCC (SDA) VCC =5.5V,fSCL=400HztWR=5ms Byte Write Page Write Write Protect VCC =5.5V,fSCL=400Hz Random Read Current Read Sequential Read VCC =5.5V,SDA,SCL= VCC A0,A1,A2=GND,WP=GND
Operating Current ICC2 0.5 mA
Standby Current
ISB
2.0
A
This product is not designed for protection against radioactive rays.
2/16
AC OPERATING CHARACTERISTICSUnless otherwise specified Ta=-4085, VCC =1.75.5V FAST-MODE 2.5VVCC5.5V Min. Typ. Max. 400 0.6 1.2 0.3 0.3 0.6 0.6 0 50 0.1 0.9 0.1 0.6 1.2 5 0.1 0 0.1 1.0 STANDARD-MODE 1.7VVCC5.5V Min. Typ. Max. 100 4.0 4.7 1.0 0.3 4.0 4.7 0 50 0.2 3.5 0.2 4.7 4.7 5 0.1 0 0.1 1.0
Parameter Clock Frequency Data Clock High Period Data Clock Low Period SDA and SCL Rise Time *1 SDA and SCL Fall Time *1 Start Condition Hold Time Start Condition Setup Time Input Data Hold Time Input Data Setup Time Output Data Delay Time Output Data Hold Time Stop Condition Setup Time Bus Free Time Write Cycle Time Noise Spike Width (SDA and SCL) WP Hold Time WP Setup Time WP High Period
Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHDWP tSUWP tHIGHWP
Unit kHz s s s s s s ns ns s s s s ms s ns s s
*1Not 100 TESTED ABOUT FAST-MODE AND STANDARD-MODE Fast-mode and Standard-mode is the same operation. So it doesn't mean the different operation. It is only distinguished by frequency of operation. It defines that the operation up to 100kHz is named "Standard-mode" and the one up to 400kHz is "Fast-mode". The value of clock frequency is maximum, it is possible to use the device up to 100kHz in Fast-mode. Lower the power supply is, more difficult it is to operate in high speed. Under Vcc=2.5V-5.5V, it is operated with 400kHz, Fast-mode (the same as Standard-mode). Under VCC=1.7V-2.5V, it is only operate with up to 100kHz. SYNCHRONOUS DATA TIMING
tR tF SCL tHD:STA SDA (IN) tBUF SDA (OUT) tPD tDH
WP
tHIGH
SCL
tSU:DAT tLOW
tHD:DAT
SDA
DATA(1) D1 D0 ACK
DATA(n) ACK
tWR
STOP BIT
Fig.1-(a) SYNCHRONOUS DATA TIMING SDA data is latched into the chip at the rising edge of SCL clock. Output data toggles at the falling edge of SCL clock.
SCL
tSUWP
WP
Fig.1-(d) WP TIMING OF THE WRITE OPERATION
SCL tSU:STA SDA START BIT tHD:STA tSU:STO
DATA(1) SDA D1 D0 ACK
DATA(n) ACK tHIGH:WP
WP
STOP BIT
Fig.1-(b) START/STOP BIT TIMING
SCL
Fig.1-(e) WP TIMING OF THE WRITE CANCEL OPERATION For the WRITE operation, WP must be "LOW" during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. (See Fig.-1 (d) ) During this period, WRITE operation is canceled by setting WP "HIGH". See Fig.-1 (e) In the case of setting WP "HIGH" during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case. 3/16
SDA
D0 ACK WRITE DATA(n) STOP CONDITION
tWR START CONDITION
Fig.1-(c) WRITE CYCLE TIMING
BLOCK DIAGRAM
A0
1
8bit
2 Kbit EEPROM ARRAY 8bit SLAVE , WORD ADDRESS REGISTER DATA REGISTER
8
VCC
A1
2
ADDRESS DECODER
8bit
7
WP
START
STOP
A2
3
CONTOROL LOGIC
ACK
6
SCL
GND
4
HIGH VOLTAGE GEN.
VCC LEVEL DETECT
5
SDA
Fig.2 BLOCK DIAGRAM PIN CONFIGURATION AND EXPLANATION PIN NAME A0 1 A1 2 BR34L02FV-W -W A2 3 GND 4 6 SCL 5 SDA 8 VCC 7 WP VCC GND A0,A1,A2 SCL SDA WP Fig.3 PIN CONFIGURATION INPUT/OUTPUT IN IN IN / OUT IN FUNCTIONS Power Supply Ground 0V Slave Address Set. Serial Clock Input Slave and Word Address, Serial Data Input, Serial Data Output *1 Write Protect Input *2
*1 An open drain output requires a pull-up resistor. *2 WP Pin has a Pull-Down resistor. Please be left unconnected or connect *2 to GND when WP feature is not in use.
CHARACTERISTICS DATA The following characteristic data are typ value.
6 5 4 VIH1,2[V] 3 2 1 0 0 1 2 3 VCC[V] 4 5 6
Ta=85 Ta=-40 Ta=25
6 5 4 VIL1,2[V] 3 2 1
SPEC Ta=85 Ta=-40 Ta=25
1 0.8 0.6
SPEC
VOL1[V]
SPEC
0.4
Ta=25
Ta=85
0.2
Ta=-40
0 0 1 2 3 VCC[V] 4 5 6
0 0 1 2 3 IOL1[mA] 4 5 6
Fig.4 "H" Input Voltage VIH1,2 (A0,A1,A2,SCL,SDA,WP)
1
Fig.5 "L" Input Voltage VIL1,2 (A0,A1,A2,SCL,SDA,WP)
1.2
SPEC
Fig.6 "L" Output Voltage VOL1-IOL1 (VCC=2.5V)
16
SPEC
0.8
1 12 0.8
Ta=85 Ta=25 SPEC
ILI1[A]
ILI2[A]
VOL2[V]
0.6
0.6 0.4
8
Ta=85 Ta=25 Ta=-40
0.4
0.2
Ta=-40
0.2 0
Ta=85 Ta=25 Ta=-40
4
0 0 1 2 3 IOL2[mA] 4 5 6
0 0 1 2 3 VCC[V] 4 5 6 0 1 2 3 VCC[V] 4 5 6
Fig.7 "L" Output Voltage VOL2-IOL2 (VCC=1.7V)
Fig.8 Input Leakage Current ILI1 (A0,A1,A2,SCL,SDA) 4/16
Fig.9 Input Leakage Current ILI2 (WP)
2.5
SPEC
0.6 0.5 0.4
=400kHz DATA=AAh Ta=85 SPEC
0.6 0.5 0.4
=100kHz DATA=AAh SPEC
2
SCL=400kHz(VCC2.5V) fSCL=100kHz(1.7VVcc2.5V) DATA=AA
ICC1[mA]
ICC2[mA]
0.3
Ta=25
ICC2[mA]
1.5
0.3 0.2
Ta=85 Ta=25 Ta=-40
1
Ta=25 Ta=85 Ta=-40
0.2
Ta=-40
0.5
0.1 0
0.1 0 0 1 2 3 VCC[V] 4 5 6 0 1 2 3 VCC[V] 4
0 0 1 2 3 VCC[V] 4 5 6
5
6
Fig.10 Write Operating Current ICC1 (fSCL=100kHz,400kHz)
Fig.11 Read Operating Current ICC2 (fSCL=400kHz)
Fig.12 Read Operating Current ICC2 (fSCL=100kHz)
2.5
SPEC
10000
2
Ta=85 Ta=25 Ta=-40
5
SPEC2
1000
4
tHIGH[s]
fSCL[kHz]
ISB[A]
1.5
SPEC1
3
100
1
SPEC2
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
2
Ta=-40 Ta=25 Ta=85
0.5
10
Ta=85 Ta=25 Ta=-40
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
1
SPEC1
0 0 1 2 3 VCC[V] 4 5 6
1 0 1 2 3 VCC[V] 4 5 6
0 0 1 2 3 VCC[V] 4 5 6
Fig.13 Standby Current ISB
Fig.14 Clock Frequency fSCL
Fig.15 Data Clock High Period tHIGH
5
SPEC2
5
SPEC2
5
SPEC2
4
4 tHD:STA[s] 3 2 1 0
0 1 2 3 VCC[V] 4 5 6
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
4 tSU:STA[s]
tLOW[s]
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
2
SPEC1 Ta=85 Ta=25 Ta=-40
2
SPEC1
1
SPEC1
Ta=-40 Ta=25 Ta=85
1
0
0
1
2
3 VCC[V]
4
5
6
0 0 1 2 3 VCC[V] 4 5
Ta=-40 Ta=25 Ta=85
6
Fig.16 Data Clock Low Period tLOW
Fig.17 Start Condition Hold Time tHD:STA
Fig.18 Start Condition Setup Time tSU:STA
50
SPEC1,2
50
SPEC1,2
200
tHD:DAT(LOW)[s]
tHD:DAT(HIGH)[ns]
-50 -100 -150 -200 0 1 2 3 VCC[V] 4
Ta=85 Ta=25 Ta=-40
-50 -100 -150
SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=85
tSU:DAT(HIGH)[ns]
0
0
100
SPEC1,2 Ta=85 Ta=25 Ta=-40
0
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
-100
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
Ta=25
Ta=-40
-200 5 6 0 1 2 3 VCC[V] 4 5 6
-200 0 1 2 3 VCC[V] 4 5 6
Fig.19 Input Data Hold Time tHD:DAT(HIGH)
Fig.20 Input Data Hold Time tHD:DAT(LOW)
Fig.21 Input Data Setup Time tSU:DAT(HIGH)
5/16
200
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
4
SPEC2
4
tSU:DAT(LOW)[ns]
100
SPEC1,2
3 tDH[s] tPD[s]
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
0
Ta=85
2
2
-100
Ta=25
Ta=-40
1
SPEC1 SPEC2 SPEC1
Ta=85 Ta=25 Ta=-40
1
SPEC2 SPEC1
Ta=85 Ta=25 Ta=-40
-200 0 1 2 3 VCC[V] 4 5 6
0 0 1 2 3 VCC[V] 4 5 6
0 0 1 2 3 VCC[V] 4 5 6
Fig.22 Input Data Setup Time tSU:DAT(LOW)
Fig.23 Output Data Delay Time tPD
Fig.24 Output Data Hold Time tDH
5
SPEC2
5
SPEC2
6
SPEC1,2
4 tSU:STO[s]
4
5 4
Ta=-40 Ta=25
tBUF[s]
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
tWR[ms]
3
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
3 2
2
2
Ta=85 Ta=25 Ta=-40
Ta=85 SPEC1:FAST-MODE SPEC2:STANDARD-MODE
1
SPEC1
0 0 1 2 3 VCC[V] 4 5
Ta=85 Ta=25 Ta=-40
1
SPEC1
1 0
0 0 1 2 3 VCC[V] 4 5 6
6
0
1
2
3 VCC[V]
4
5
6
Fig.25 Stop Condition Setup Time tSU:STO
Fig.26 Bus Free Time tBUF
Fig.27 Write Cycle Time tWR
0.6 0.5 0.4 0.3
Ta=85 SPEC1:FAST-MODE SPEC2:STANDARD-MODE
0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 VCC[V] 4 5 6 0 1 2 3 VCC[V] 4 5 6
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
0.6 0.5 tI(SDA H)[s] 0.4 0.3 0.2 0.1 0 0 1 2 3 VCC[V] 4 5 6
Ta=25 SPEC1:FAST-MODE SPEC2:STANDARD-MODE
tI(SCL H)[s]
Ta=25
Ta=-40
tI(SCL L)[s]
Ta=-40
Ta=-40 Ta=25
0.2
SPEC1,2
Ta=85
Ta=85 SPEC1,2 SPEC1,2
0.1 0
Fig.28 Noise Spike Width tI(SCL H)
Fig.29 Noise Spike Width tI(SCL L)
Fig.30 Noise Spike Width tI(SDA H)
0.6 0.5 0.4 0.3 0.2 0.1
SPEC1,2 Ta=25 Ta=-40 SPEC1:FAST-MODE SPEC2:STANDARD-MODE
0.2
SPEC1,2
1.2 1 tHIGH:WP[ s] 0.8 0.6 0.4 0.2 0 0 1 2 3 VCC[V] 4 5 6 0 1 2 3 VCC[V] 4 5 6
Ta=-40 Ta=25 Ta=85 SPEC1:FAST-MODE SPEC2:STANDARD-MODE SPEC1,2
0 tSU:WP[s]
SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=25 Ta=85
tI(SDA L)[s]
-0.2
Ta=85
-0.4
Ta=-40
0 0 1 2 3 VCC[V] 4 5 6
-0.6
Fig.31 Noise Spike Width tI(SDA L)
Fig.32 WP Setup Time tSU:WP
Fig.33 WP High Period tHIGH:WP
6/16
2 Data transfer on the I C-bus 2 Data transfer on the I C-bus The bus considered to be busy after the START condition, and be free again a certain time after the STOP condition. Every byte put on the SDA line must be 8-bits long, and after each byte, the signal of a acknowledge is obligatory. The devices have the master and slave. The master is the device which initiates and ends a data transfer on the bus and generates the clock signals to permit that transfer. The slave is the device which controlled with the unique address. EEPROM is slave. Also the device transmitting during transferring the data is called transmitter, and the device received is called receiver.
START CONDITION (RECOGNITION OF START BIT) All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Fig.1-(b) START/STOP BIT TIMING STOP CONDITION (RECOGNITION OF STOP BIT) All commands must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. See Fig.1-(b) START/STOP BIT TIMING ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is -COM. When outputting the data in the read operation, it is this device.) During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that the eight bits of data has been received. (When inputting the slave address in the write or read operation, receiver is this device. When outputting the data in the read operation, it is -COM.) The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit). In the WRITE mode, the device will respond with an Acknowledge, after the receipt of each subsequent 8-bit word (word address and write data). In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an Acknowledge. If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. DEVICE ADDRESSING Following a START condition, the master output the slave address to be accessed. The most significant four bits of the slave address are the "device type indentifier," for the device this is fixed as "1010." (In access to WP register, this code use "0110".) The next three bit (device address) identify the specified device on the bus. The device address is defined by the state of A0,A1 and A2 input pins. This IC works only when the device address inputted from SDA pin correspond to the state of A0,A1 and A2 input pins. Using this address scheme, up to eight devices may be connected to the bus. The last bit of the stream (R/W...READ/WRITE) determines the operation to be performed. R/W=0 R/W=1 Device Type 1010 0110 WRITE (including word address input of Random Read) READ Device Address A2 A1 A0 A2 A1 A0
R/W R/W
Access to Memory Access to Write Protect Register
7/16
WRITE PROTECT COMMAND Write Protect Command is to cancel any write command which access to the address007Fh. Write Protect Register can be written for once (Onetime Rom). Once this command is excuted, the data is protected forever. WRITE PROTECT PIN(WP) When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level), it is enable to write 256 words (all address). If permanent protection is done by Write Protect command, lower half area (007Fh address) is inhibited writing regardless of WP pin state. WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use. COMMAND WRITE CYCLE With WRITE CYCLE operation, the given data is written in the EEPROM. BYTE WRITE CYCLE is usually used to write only one byte, but in case of writing continuous data more than one byte, it is possible with PAGE WRITE. The maximum bytes written at once is up to 16 bytes.
S T A R T SDA LINE
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
W R I T E WA 7 RA /C WK
WORD ADDRESS WA 0 A C K D7
DATA
S T O P D0 A C K
Fig.34 BYTE WRITE CYCLE TIMING
S T A R T SDA L IN E
S LA V E ADDRESS 1 0 1 0 A 2A 1A 0
W R I T E WA 7 RA /C WK
W ORD A D D R E S S (n ) WA 0 A C K D7
D A TA (n) D0 A C K
D A TA (n + 1 5) D0 A C K
S T O P
Fig.35 PAGE WRITE CYCLE TIMING By using this command, the data is programmed into the indicated word address. When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array. This device is capable of sixteen byte Page Write operation. Once the programming is started, any commands isn't accept for tWR (5ms max.). If the master transmits more than sixteen words, prior to generating the STOP condition, the address counter will "roll over," and the previous transmitted data will be overwritten. When two or more byte data are inputted, the four low order address bits are internally incremented by one after the receipt of each word. The four higher order bits of the address(WA7WA4) remain constant.
8/16
COMMAND READ CYCLE With READ CYCLE operation, the data is read from the EEPROM. READ CYCLE has RANDOM READ CYCLE and CURRENT READ CYCLE. RANDOM READ CYCLE is usually used to read the data in the indicated address. Also CURRENT READ CYCLE is used to read the data in the address indicated internally and make a role of verifying the data immediately after WRITE OPERATION. The Sequential Read operation can be performed with both Current Read and Random Read. With SEQUENTIAL READ CYCLE, it is possible to read the next data continuously. It is necessary to input "high" at last ACK timing.
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0 A C K RA /C WK R E A D D7 S T O P D0 A C K
S T A R T SDA L IN E
S LA V E ADDRESS 1 0 1 0 A 2 A 1A 0
W R I T E WA 7 RA /C WK
W ORD A D D R E S S (n) WA 0
S T A R T
D A TA (n )
Fig.36 RANDOM READ CYCLE TIMING
S T A R T SDA LINE R E A D D7 RA /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
DATA
It is necessary to input "high" at last ACK timing.
Fig.37 CURRENT READ CYCLE TIMING Random Read operation allows the master to access any memory location indicated by word address. In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). If an Acknowledge is detected, and no STOP condition is generated by the master (-COM), the device will continue to transmit the data. It can transmit all data (2kbit 256word) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition.
S T A R T SDA L IN E R E A D S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
D A T A (n ) D7 D0 A C K A C K D7
D A T A (n + x)
It is necessary to input "high" at last ACK timing.
RA /C WK
Fig.38
SEQUENTIAL READ CYCLE TIMING With Current Read
If an Acknowledge is detected, and no STOP condition is generated by the master (-COM), the device will continue to transmit the data. It can transmit all data (2kbit 256word) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition.
9/16
SOFTWARE RESET Please execute software reset in case that the device is an unexpected state after power up and/or the command input need to be reset. There are some kinds of software reset. Here we show three types of example as follows. During dummy clock, please release SDA bus (tied to VCC by pull up resistor) . During that time, the device may pull the SDA line LOW for acknowledge or outputting read data. If the master controls the SDA line HIGH, it will conflict with the device output LOW then it makes a current overload. It may cause instantaneous power down and may damage the device.
DUMMY CLOCKx14 STARTx2
SCL SDA
1
2
13
14
COMMAND COMMAND
Fig.39-(a) DUMMY CLOCKx14 + START+START
START DUMMY CLOCKx9 START
SCL SDA
1
2
8
9
COMMAND COMMAND
Fig.39-(b) START + DUMMY CLOCKx9 + START
STARTx9
SCL SDA
1
2
3
7
8
9
COMMAND COMMAND
Fig.39-(c) STARTx9 * COMMAND starts with start condition. ACKNOWLEDGE POLLING Since the device ignore all input commands during the internal write cycle, no ACK will be returned. When the master send the next command after the write command, if the device returns the ACK, it means that the program is completed. If no ACK is returned, it means that the device is still busy. By using Acknowledge polling, the waiting time is minimized less than tWR=5ms. In case of operating Write or Current Read after Write, first, send the slave address (R/W is"HIGH" or "LOW" respectively). After the device returns the ACK, continue word address input or data output respectively. During the internal write cycle, no ACK will be returned. (ACK=HIGH)
S T A R T
THE FIRST WRITE COMMAND
S T A R T
WRITE COMMAND
S O P
SLAVE ADDRESS
A C K H
S T A R T
SLAVE ADDRESS
A C K H
tWR
THE SECOND WRITE COMMAND
S T A R T
SLAVE ADDRESS
A C K H
S T A R T
SLAVE ADDRESS
A C K L
WORD ADDRESS
A C K L
DATA
A C K L
S O P
tWR
After the internal write cycle is completed, ACK will be returned (ACK=LOW). Then input next Word Address and data.
Fig.40 SUCCESSIVE WRITE OPERATION BY ACKNOWLEDGE POLLING
10/16
WP EFFECTIVE TIMING WP is fixed to "H" or "L" usually . But in case of controlling WP to cancel the write command, please pay attention to "WP effective timing" as follows. During write command input , write command is canceled by controlling WP "H" within the WP cancellation effective period. The period from the start condition to the rising edge of the clock which take in DO of the data (the first byte of the data for Page Write) is the cancellation invalid period. WP input is don't care during the period. Setup time for rising edge of the SCL which takes in DO must be more than 100ns. The period from the rising edge of SCL which takes in DO to the end of internal write cycle (tWR) is the cancellation effective period. In case of setting WP to "H" during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed, so that write correct data again please. It is not necessary waiting tWR (5msMax.) after stopping command by WP, because the device is standby state.
The
rising edge of the clock which take in DO
SCL SDA D0 ACK
SCL D1 SDA D0 ACK
The rising edge of SDA
AN ENLARGEMENT
A A C C K D7 D6 D5 D4 D3 D2 D1 D0 K L L
AN ENLARGEMENT
SDA
S A T SLA VE C WORD A K R ADDRESS L ADDRESS T
DATA
A C K L
S T O P
tWR
WP cancellation
WP cancellation effective period
Stop of the write operation Data is not
WP
invalid period
No data will be written
guaranteed
Fig.41 WP EFFECTIVE TIMING
COMMAND CANCELLATION BY START AND STOP CONDITION During a command input, it is canceled by the successive inputs of start condition and stop condition.(Fig.42) But during ACK or data output, the device may output the SDA line LOW. In such cases, operation of start and stop condition is impossible, so that the reset can't work. Execute the software reset in the cases. (Fig.39) Operating the command cancel by start and stop condition during the command of Random Read or Sequential Read or Current Read, internal address counter is not confirmed. Therefore operation of Current Read after this is not valid. Operate a Random Read in this case.
SCL
SDA
1
0
1
0
START CONDITION STOP CONDITION
Fig.42 COMMAND CANCELLATION BY START AND STOP CONDITION DURING THE INPUT OF SLAVE ADDRESS
11/16
I/O CIRCUIT PULL UP RESISTOR OF SDA PIN The pull up resistor is needed because SDA is NMOS open drain. Decide the value of this resistor(RPU) properly, by considering VIL, IL characteristics of a controller which control the device and VOL-IOL characteristics of the device. If large RPU is chosen, clock frequency need to be slow. In case of small RPU , the operating current increases. MAXIMUM OF RPU Maximum of RPU is determined by following factors. SDA rise time determined by RPU and the capacitance of bus line(CBUS) must be less than tR. And the other timing must keep the conditions of AC specification. When SDA bus is HIGH, the voltage A of SDA bus determined by a total input leakage(IL) of the all devices connected to the bus and RPU must be enough higher than input HIGH level of a controller and the device, including noise margin 0.2VCC. VCC-ILRPU-0.2 VCC VIH RPU 0.8VCC-VIH IL
IL MICRO COMPUTER RPU A SDA PIN BR34L02
Examples: When VCC =3V, IL=10A, VIH=0.7 VCC According to RPU 0.8x3-0.7x3 -6 10x10
IL
300 k
THE CAPACITANCE OF BUS LINE (CBUS)
THE MINIMUM VALUE RPU The minimum value of RPU is determined by following factors. Meet the condition that VOLMAX=0.4V, IOLMAX=3mA when the device output low on SDA line. VCC-VOL IOL RPU RPU VCC-VOL IOL
Fig.43 I/O CIRCUIT
VOLMAX(=0.4V) must be lower than the input LOW level of the controller and the EEPROM including recommended noise margin(0.1VCC). VOLMAX VIL-0.1 VCC Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC, According to RPU 3-0.4 3x10 -3
867 and VOL=0.4V And VIL=0.3x3 =0.9V so that condition is met PULL UP RESISTOR OF SCL PIN In the case that SCL is controlled by CMOS output, the pull up resistor of SCL is not needed. But in the case that there is a timing at which SCL is Hi-Z, connect SCL to VCC with pull up resistor.
Severalseveral dozen k is recommended as a pull up resistor, which is considered with the driving ability of the output port of the controller.
CONNECTIONS OF A0, A1, A2, WP PIN CONNECTIONS OF DEVICE ADDRESS PIN(A0, A1, A2) The state of device address PIN are compared with the device address send by the master, then one of the devices which are connected to the identical bus is selected. Pull up or down these pins, or connect them to VCC or GND. Pins which is not used as device address (N.C.PIN) may be either HIGH, LOW, and Hi-Z. CONNECTIONS OF WP PIN The WP input allows or inhibits write operations. When WP is HIGH, only READ is available and WRITE to any address is inhibited. Both Read and Write are available when WP is LOW. In the case that the device is used as a ROM, it is recommended that WP is pulled up or connected to VCC. In the case that both READ and WRITE are operated, WP pin must be pulled down or connected to GND or controlled. 12/16
THE NOTICE ABOUT THE CONNECTION OF CONTROLLER ABOUT Rs 2 The open drain interface is recommended for SDA port in I CBUS. But, in the case that Tri-state CMOS interface is applied to SDA, insert a series resistor Rs between SDA pin of the device and a pull up resistor RPU. It limits the current from PMOS of controller to NMOS of EEPROM. Rs also protects SDA pin from surges. Therefore, Rs is able to be used though SDA port is open drain.
ACK
RPU
SCL
RS
SDA
'H'OUTPUT OF CONTROLLER
"L" OUTPUT OF EEPROM
CONTROLLER
EEPROM
The "H" output of controller and the "L" output of EEPROM may cause current overload to SDA line.
Fig.44 I/O CIRCUIT
Fig.45 INPUT/OUTPUT COLLISION TIMING THE MAXIMUM VALUE OF Rs The maximum value of Rs is determined by following factors. SDA rise time determined by RPU and the capacitance of bus line(CBUS) of SDA must be less than tR. And the other timing must also keep the conditions of the AC timing. When the device outputs LOW on SDA line, the voltage of the bus A determined by RPU and Rs must be lower than the inputs LOW level of the controller, including recommended noise margin(0.1VCC).
VCC RPU A RS IOL
BUS CAPACITANCE
(VCC-VOL)xRS RPU+RS
VOL
+ VOL+0.1VCCVIL VIL-VOL-0.1VCC 1.1VCC-VIL
RS
x
RPU
Examples : When VCC=3VVIL=0.3VCCVOL=0.4VRPU=20k
EEPROM
VIL
CONTROLLER
According to RS
0.3x3-0.4-0.1x3 1.1x3-0.3x3
x
20x10
3
Fig.46 I/O CIRCUIT
1.67k
THE MINIMUM VALUE OF Rs The minimum value of Rs is determined by the current overload due to the conflict on the bus. The current overload may cause noises on the power line and instantaneous power down. The following conditions must be met, where I is the maximum permissible current. The maximum permissible current depends on Vcc line impedance and so on. It need to be less than 10mA for EEPROM.
Vcc RS RS RPU "L" OUTPUT I Vcc I
RS
MAXIMUM CURRENT
Examples: When VCC=3V, I=10mA RS 3 -3 10x10
"H" OUTPUT
300 EEPROM
CONTROLLER
Fig.47 I/O CIRCUIT 13/16
2 I C BUS INPUT / OUTPUT CIRCUIT
INPUT(A0,A2,SCL)
Fig.48 INPUT PIN CIRCUIT INPUT / OUTPUT (SDA)
Fig.49 INPUT / OUTPUT PIN CIRCUIT INPUT (A1)
Fig.50 INPUT PIN CIRCUIT INPUT (WP)
Fig.51 INPUT PIN CIRCUIT
14/16
NOTES FOR POWER SUPPLY VCC rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device may not work properly due to an incomplete reset of internal circuit. To prevent this, the device has the feature of P.O.R. and LVCC. In the case of power up, keep the following conditions to ensure functions of P.O.R. and LVCC. 1. It is necessary to be "SDA='H'" and "SCL='L' or 'H'". 2. Follow the recommended conditions of tR, tOFF, Vbot for the function of P.O.R. during power up.
VCC tR
Recommended conditions of tR, tOFF, Vbot tR tOFF Vbot
tOFF
Below 10ms
Vbot
Above 10ms Below 0.3V
Below 100ms Above 10ms Below 0.2V
0
Fig.52 VCC rising wavefrom
3. Prevent SDA and SCL from being "Hi-Z". In case that condition 1. and/or 2. cannot be met, take following actions. AUnable to keep condition 1.( SDA is "LOW" during power up.) Control SDA ,SCL to be "HIGH" as figure below.
VCC SCL
tLOW
SDA After Vcc becomes stable tDH tSU:DAT After Vcc becomes stable tSU:DAT
Fig.53 SCL="H" and SDA="L"
Fig.54 SCL="L" and SDA="L"
BUnable to keep condition 2. After power becomes stable, execute software reset. (See page 10/16) CUnable to keep both conditions 1 and 2. Follow the instruction A first, then the instruction B. LVCC CIRCUIT LVCC circuit inhibit write operation at low voltage, and prevent an inadvertent write. Below the LVCC voltageTyp.=1.2V, write operation is inhibited. NOTES FOR NOISE ON VCC ABOUT BYPASS CAPACITOR Noise and surges on power line may cause the abnormal function. It is recommended that the bypass capacitors (0.1F) are attached on the VCC and GND line beside the device. The attachment of bypass capacitors on the board near by connector is also recommended. CAUTIONS ON USE (1)Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (2) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (3) Thermal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (4) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (5) Use in a strong electromagnetic field may cause malfunction, therefore, evaluated design sufficiently.
15/16
SELECTION OF ORDER TYPE
BR
34
L
02
FV
W
E2
ROHM type BUS type 34:I C
2
Product type L:1.8Vversion *
Capacity Package 02=2K FV:SSOP-B8 FVT:TSSOP-B8
Double Cell
Package specifications E2:reel shape emboss taping
*1.7V version only for BR34L02-W
PACKAGE SPECIFICATIONS
SSOP-B8/TSSOP-B8

SSOP-B8
3.00.2
8 5
TSSOP-B8
SSOP-B8/TSSOP-B8 Embossed carrier tape Tape Quantity 2500pcs Direction of feed E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
6.40.3 4.40.2
1
4
0.150.1 0.1
1.150.1 0.1
0.220.1
0.3Min.
1234
1234
1234
1234
1234
1234
1234
1234
(0.52)
0.65
Reel
1pin
Direction of feed
Unit:mm)
When you order , please order in times the amount of package quantity.
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office.
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Copyright (c) 2007 ROHM CO.,LTD.
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Appendix1-Rev2.0

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